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NXP Semiconductors /LPC18xx /I2S0 /IRQ

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Interpret as IRQ

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_IRQ_ENABLE)RX_IRQ_ENABLE 0 (TX_IRQ_ENABLE)TX_IRQ_ENABLE 0RESERVED0RX_DEPTH_IRQ 0RESERVED 0TX_DEPTH_IRQ 0RESERVED

Description

I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.

Fields

RX_IRQ_ENABLE

When 1, enables I2S receive interrupt.
TX_IRQ_ENABLE

When 1, enables I2S transmit interrupt.
RESERVED

Reserved.
RX_DEPTH_IRQ

Set the FIFO level on which to create an irq request.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
TX_DEPTH_IRQ

Set the FIFO level on which to create an irq request.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data